Skip to content
GitLab
Explore
Sign in
Explore
Projects
Explore projects
All
Most starred
Trending
Verilog
Any
Assembly
C
C++
Forth
HTML
M4
Makefile
Objective-C
Shell
TeX
Verilog
Most stars
Sort by
Updated date
Last created
Name
Name, descending
Most stars
Oldest updated
Oldest created
Hide archived projects
Show archived projects
Show archived projects only
B
Bernd Paysan /
b16-small
b16 Forth CPU, small variant
1
Updated
Dec 29, 2019
1
0
0
0
Updated
Dec 29, 2019
B
Bernd Paysan /
b16
b16 simple Forth CPU
1
Updated
Jun 09, 2018
1
0
0
0
Updated
Jun 09, 2018